Design of Decimation Filters for Wireless Local Area Network Applications

Kantharaj S P, G S Sunitha, G H Leela, S O Nirmala


Multirate signal processing is critical to realizing the digital frequency converter in WLAN technologies. In this paper, we focus on designing and analyzing the different structures of decimators that support WLAN-b applications to reduce the frequency by 12 for an IEEE. The structure modeling of the decimator used Simulink. Implementing a single-stage decimator required a higher-order filter, extra storage space, and a long simulation time. Results showed that the necessary storage elements for 2-stage design are 55% and for 3-stage design is 65% of single stage. For 133 MHz WLAN-b application, a two-stage decimator is proved to be efficient.


Sampling Rate Conversion; WLAN-b; FIR Filter; Decimator

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V. Jayaprakasan and K. Pavitra, “Comparative Analysis ofInterpolation/ Decimation FIR Filter Structuresfor WLAN-b and WLAN-g Applications,” Int. J. Innov. Res. Sci. Technol., vol. 2, no. 2, 2016.

R. E. Crochiere and L. R. Rabiner, “Interpolation and Decimation of Digital Signals-A Tutorial Review,” Proc. IEEE, vol. 69, no. 3, pp. 300–331, 1981, doi: 10.1109/PROC.1981.11969.

M. Sabraj, “Spectral Analysis of Sample Rate Converter,” Sign. Processing: An Intern. J. (SPIJ), vol. 4, no. 4. pp. 219-227, 2014.

Arunkumar and K. Ganesh, “Performance and Analysis of Transmultiplexers,” J. Circuits, Syst. Comput., vol. 28, no. 1, pp. 1–8, 2019, doi: 10.1142/S0218126619500099.

S. A. Kumar and P. G. Kumar, “Elegant and Practical Method of Fir Decimation Using Comb Filters in the Field of Digital Signal Processing,” Circuits Syst., vol. 7, no. 9, pp. 2476–2488, 2016, doi: 10.4236/cs.2016.79214.

V. M. Student, “Sub Band Coding of Speech Signal by using Multi-Rate Signal Processing,” vol. 2, no. 9, pp. 45–49, 2013, [Online]. Available:

N. B. Bahadure, “Multirate Digital Signal Processing System for Digital Communication Multirate Digital Signal Processing System for Digital Communication,” no. 1, pp. 1–2, 2016.

S. Xu, Y. Chai, Y. Hu, L. Huang, and L. Feng, “The analysis of decimation and interpolation in the linear canonical transform domain,” Springerplus, vol. 5, no. 1, 2016, doi: 10.1186/s40064-016-3479-4.

S. Sarswat and M. Kaur, “Decimation Filter Design Optimization of ADC for ECG Processing,” IOSR J. Electr. Electron. Eng., vol. 13, no. 2, pp. 63–66, 2018, doi: 10.9790/1676-1302036366.

P. E. Howland, D. Maksimiuk, and G. Reitsma, “FM radio based bistatic radar,” IEE Proc. Radar, Sonar Navig., vol. 152, no. 3, pp. 107–115, 2005, doi: 10.1049/ip-rsn:20045077.

G. G. Moon and S. N. Joshi, “Design Approach for Decimation Filter for ADC Application,” Int. J. Eng. Trends Technol., vol. 10, no. 12, pp. 597–600, 2014, doi: 10.14445/22315381/ijett-v10p320.

K. H. Abed and S. Colaco, “Design and Implementation of a Decimation Filter For High Performance Audio Applications,” pp. 812–815, 2007.

Q. Jing, Y. Li, and J. Tong, “Performance analysis of multi-rate signal processing digital filters on FPGA,” Eurasip J. Wirel. Commun. Netw., vol. 2019, no. 1, 2019, doi: 10.1186/s13638-019-1349-9.

S. Kim, J. Oh, and D. Hong, “Design of Low Area Decimation Filters Using CIC Filters,” vol. 20, no. 3, pp. 71–76, 2021.

A. V. Babu and L. Jacob, “Fairness analysis of IEEE 802.11 multirate wireless LANs,” IEEE Trans. Veh. Technol., vol. 56, no. 5, pp. 3073–3088, 2007, doi: 10.1109/TVT.2007.898397.

J. G. Proakis, Digital Signal Processing, 4th Edition, 4th ed. Massachusetts: Massachusetts Institute of Technology, Lincoln Laboratory, 2007.

F. Francesconi, G. Lazzari, V. Liberali, F. Maloberti, and G. Torelli, “A novel interpolator architecture for ΣΔ DACs,” no. March, pp. 249–253, 2002, doi: 10.1109/edac.1993.386468.

G. S. Gawande, Khanchandani, and Marode, “Performance analysis of FIR digital filter design techniques,” Int. J. Comput. Corp. Res., vol. 2, no. 1, 2012.

G. S. Gawande, B. Pawar, and Khanchandani, “Performance Evaluation of Efficient Structure for Fir Decimation Filters Using Polyphase Decomposition Technique,” Inter. J. Electron. Commun. Eng. Technol. (IJECET), vol. 6, no. 5, pp. 1–8, 2015.

M. P. Chaudhari and M. T. Pce, “The Fir Filter Design and Analysis and Code Generation Using HDLCODER for Area and Power Efficient FPGA Implementation,” Int. J. Emerg. Technol. Eng. Res., vol. 4, no. 7, pp. 99–102, 2016.


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